Tests on semiconductor integrated circuits are broadly divided into tests (hereinafter referred to as “probe tests”) which are performed on semiconductor integrated circuits in wafer form after completion of diffusion process and tests which are conducted on semiconductor integrated circuits as packaged products after completion of assembly process.
A probe test is performed by placing a probe card in prober equipment and bringing the probe needles of the probe card into contact with electrode pads on IC chips which are connected with an LSI tester and arranged regularly on a wafer.
FIG. 10 is a view illustrating the structure of a typical probe card. In FIG. 10, the reference numeral 101 refers to a probe card substrate, and the reference numerals 102a, 102b, . . . refer to probe needles. The numerous probe needles 102a, 102b, . . . are connected at their base ends to the probe card substrate 101, while their tip ends protrude obliquely downward. The base ends of the probe needles 102a, 102b, . . . are electrically connected to an LSI tester via the probe card substrate 101. The tip end of each of the probe needles 102a, 102b, . . . corresponds to the approximate center of an electrode pad of a semiconductor integrated circuit.
Patent Document 1 discloses a technique in which the positions and levels of all probe needles with respect to electrode pads are automatically recognized by aligning a reference position for LSI chips with a reference position in probe needle information.
Patent Document 1: Japanese Laid-Open Publication No. 2005-150224